The invention relates to reducing bus loading due to snoop traffic.
Referring to FIG. 1, a typical computer system 10 may include a level one (L1) cache 14 to expedite transactions between a microprocessor 16 and a system memory 18, such as a dynamic random access (DRAM) memory. To accomplish this, the cache 14 typically includes a static random access memory (SRAM) that typically is more expensive and faster than the system memory 18. Usually, the cache 14 retains a copy of data in the most recently accessed (by the microprocessor 16) memory locations to make these locations xe2x80x9ccached locations.xe2x80x9d In this manner, when the microprocessor 16 executes a memory read operation, for example, to retrieve data from one of the cached locations, the cache 14, instead of the system memory 18, provides the data to the microprocessor 16. As a result, the read operation is accomplished in less time than if the data is retrieved from the slower system memory 18. Because of the cache 14, memory write operations by the microprocessor 16 may also be accomplished in less time, as the data may be stored in the cache 14 instead of in the system memory 18. The cache 14 typically is integrated with the microprocessor 16 and may be accessed by devices other than the microprocessor 16 via a local bus 22 that is coupled to the microprocessor 16.
Because devices other than the microprocessor 16 typically interact with the system memory 18, measures typically are in place to preserve coherency between data stored in the cache 14 and data stored in the system memory 18. For example, a bridge 23 may furnish a memory write operation to a cached location. In short, the cache 14 may implement a variety of different protocols to preserve data coherency.
For example, for a xe2x80x9cwrite-throughxe2x80x9d protocol, the write operation furnished by the bridge 23 in the above example causes the cache 14 to invalidate a corresponding cache line in the cache 14. A cache line typically includes several bytes of data that are associated with contiguous memory locations. When the microprocessor 16 executes a memory write operation that targets a memory location that is associated with a cache line, then a xe2x80x9cwrite hitxe2x80x9d occurs. In general, to determine when a cache hit (i.e., a write or read (described below) hit) occurs, a bus operation called xe2x80x9csnoopingxe2x80x9d occurs on the local bus 22. In response to this write hit, the cache 14 updates the corresponding cache line and the corresponding locations in the system memory 18 pursuant to the write-through policy. However, when a device other than the microprocessor 16 writes to a memory location that is associated with the cache line, then the cache 14 invalidates the cache line, as at least some of the data of the cache line has become xe2x80x9cstale.xe2x80x9d Read operations are handled in a slightly different manner. When the microprocessor 16 executes a memory read operation, the cache 14 determines if a xe2x80x9cread hitxe2x80x9d occurs. A read hit occurs if the read operation targets a memory location that is associated with a cache line that has not been invalidated. When a read hit occurs, the cache 14 (and not the slower system memory 18) provides the requested data. Otherwise, the system memory 18 provides the requested data.
The cache 14 may alternatively implement a xe2x80x9cwrite-backxe2x80x9d policy that improves the performance of memory write operations (versus the xe2x80x9cwrite-throughxe2x80x9d policy described above) by eliminating the slower writes to system memory 18 every time the cache 14 is updated. Instead, the system memory 18 is updated when coherency problems arise. In this manner, when the microprocessor 16 writes data to a memory location associated with a cache line, a write hit occurs, and in response to this occurrence, the cache 14 updates the corresponding cache line without updating the system memory 18. When a device other than the microprocessor 16 performs a memory write operation to a memory location that is associated with the cache line, then the cache 14 does not invalidate the associated cache line, as some of the data in the cache line may have been modified by the microprocessor 16. Instead, the cache 14 halts, or xe2x80x9cbacks off,xe2x80x9d the memory write operation and updates the memory locations in the system memory 18 that are associated with the cache line. After the system memory 18 is updated, the cache 14 permits the original write operation to proceed. For the write-back policy, a similar scenario occurs when a device other than the microprocessor 16 performs a read operation to read data from the system memory 18.
The memory write operations that are furnished by the bridge 23 may be, for example, in response to a stream of data that is produced by video camera 12. In this manner, the video camera 12 may continually provide signals indicative of frames of data to a serial bus 11 that is coupled to the bridge 23. In response, the bridge 23, in turn, may generate numerous write operations to store the data in predetermined contiguous regions of the system memory 18 where the data may be processed (decompressed, for example) by the microprocessor 16 before corresponding video images are formed on a display 20.
Unfortunately, the numerous write operations that are furnished by the bridge 23 may cause an extensive number of snooping operations on the local bus 22. The snooping operations, in turn, may consume a considerable amount of bandwidth of the local bus 22. As a result, the processing bandwidth of the microprocessor 16 may be effectively reduced.
Thus, there is a continuing need for a computer system to more efficiently handle a stream of data.
In one embodiment, a method for use with a computer system includes receiving requests to store data in one or more memory locations that are collectively associated with a cache line. The requests are combined to furnish a memory operation.